Vc, Perl, Verilog, Python, System Verilog, Tcl, LINT, cdc, Vlsi, front-end design verification techniques, formal verification tools, LEC, spyglass, FV, Synthesis, RDC, Design Compilers, EDA Tools, ASIC Design

Java, C, multithreading, Python, AI tools, LSF concepts, debugging skills, EDA flow Automation, multiprocessing

redhawk , Shell, PERL, Verilog, Tcl, place and route methodologies, low power physical design flows and methodologies, Fusion Compiler, physical implementation and analysis tools, timing and signal integrity analysis, Innovus, Calibre, VHDL, power integrity and reliability analysis, power grid planning and implementation, Starrcxt, timing optimization and timing closure, placement and optimization, metal-only ECO implementation, floorplan exploration and optimization, Clock Tree Synthesis

hardware engineering , Automation, Deep sub-micron technology, Multi-voltage domains, Circuit Design, Power gating, UPF, Physical Design, Synthesis, ASIC design flows, Sign-off optimizations, PNR, device physics, Low power design implementation

static timing analysis, Digital Logic Design, Perl, Verilog, Python, Scripting, Tcl, Synthesis, cdc, memory subsystems, SOC design, Uvm, IP integration, systemverilog, Rtl Design, Axi, formal verification, EDA tool flows, LINT, Verification, Microarchitecture, bus architectures, automation of design flows

static timing analysis, Floor Planning, Synthesis, Makefile scripting, physical design CAD flow, physical design verification, Mentor Calibre, Power Distribution, Cadence Innovus, Cadence Genus

Rtos, Embedded Linux, Uart, Spi, Git, Ipc Mechanisms, I2c, C Programming, Python, BACnet, Modbus, Linux process management

clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, PNR Floor Plan, Power Mesh, Timing Signoff

Verilog, multi-clock designs, Synthesis, formal verification, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Timing Concepts, asynchronous interfaces, System-Verilog