Vcs, DDR, Shell, Pcie, Perl, Ethernet, Python, Verdi, CHI, IUS, Uvm, systemverilog, Axi, Questa, AHB

Mac, Pcie, Switches, Ethernet, FPGA verification, RDMA, NICs, SmartNICs, networking architectures, Uvm, systemverilog

Vcs, Git, Pcie, Ethernet, System Verilog, low-power verification techniques, cdc, Uvm, UPF, C Language, Axi, level shifter implementation, AMBA, FIFOs, APB, Questa, RISC-V CPU subsystems, clock reset architectures, power management strategies, AHB

Cpu, Ethernet, Pcie, Debugging, DDR, Uvm, Assertions, SoC Integration, SV, Coverage Closure, Complex Verification Flows, RISC-V, formal verification, IP Sub-System SoC DV Testbench Development

Spi, I2c, Gpio, Uart, Pcie, DDR, UVM methodology, I3C, QSPI, CXL, systemverilog, HBM

cache coherency , Uvm, DMA engines, ARM-based SoCs, memory systems, systemverilog, Transaction-level verification, CHI, Ace, AXI NoC architectures

code coverage , Nvme, System Verilog, Ethernet, Pcie, DDR, Uvm, UCIe, simulation and debug tools, AHB, assertions, functional coverage, CXL, APB, Axi

IP SoC verification, ASIC-SoC design verification, systemverilog

code coverage , Fpga, Ovm, Test Cases, Hdl, Shell, Pcie, Verilog, Debugging, System Verilog, Python, Perl, Pci, Sta, test benches, RTL, Uvm, DDR PHY, Ethernet MAC, VHDL, ASIC, RTL top level integration, Functional coverage, Frontend Design, Logic Synthesis, HVL