Fpga, Perl, Python, low power verification, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, RTL development environments, transaction level modelling, test bench infrastructure, verification platforms, formal verification methods, emulation platforms

Fpga, Perl, Python, low power verification, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, RTL development environments, test bench infrastructure, transaction level modelling, verification platforms, formal verification methods, emulation platforms

Perl, Python, verification methodologies, low power verification, system level performance analysis, Uvm, systemverilog, RTL development environments, test bench infrastructure, emulation platforms, test plan development, automation scripts

Perl, Python, RTL development environments, test bench infrastructure, low power verification, verification methodologies, system level performance analysis, emulation platforms, Uvm, automation scripts, systemverilog

redhawk , PDN methodology, PNR and signoff tools, Cadence Innovus, Physical Verification, IR EM mitigation, floorplanning, STA constraints, physical design implementation, primetime, Synopsys ICC2, Tempus, Voltus