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Showing 3 jobs
Skills:
Python, scoreboarding, Mentor Questa, Cadence Xcelium, AXI protocol, SystemVerilog UVM, GLS, Synopsys VCS, memory controller architecture, assertions SVA, DDR protocol JEDEC specifications, functional coverage
Skills:
Python, scoreboarding, Mentor Questa, Cadence Xcelium, AXI protocol, GLS, SystemVerilog UVM, Synopsys VCS, memory controller architecture, assertions SVA, DDR protocol JEDEC specifications, functional coverage
Skills:
Digital Logic Design, Embedded Firmware, Scripting Languages, Verilog, System Verilog, Jtag, IEEE1500, MBIST, UPF, Memory dump, Scan dump, DFT architecture, Power management verification, Micro-processor debug, C Language, Hardware
