redhawk , Tcl, Routing, Python, Perl, Multi-voltage domains, Foundry PDKs, UPF, Timing Closure, Signoff, Cadence Innovus, Power gating, floorplanning, primetime, Tempus, Synopsys ICC2, CPF, Voltus, Placement, Physical Design, Samsung, Low-power design techniques

Debugging, Logic Design, Sta, Circuit Design, Physical Verification, PNR, Physical Design, EDA Tools, Optimization, Rtl Design

redhawk , Perl, Python, Tcl, EMIR sign-off flows, Voltus, electromigration analysis, Totem, chip-package co-simulation, EMIR sign-off methodology, chip-package co-design, PDN planning, PDN architecture planning

physical verification using ICV, Innovus, VLSI Physical Design flows, Fusion Compiler, Synopsys Cadence Physical Design tools

Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology

Python, Tcl, Synopsys IC Validator, Cadence PVS, primetime, Fusion Compiler, Cadence Innovus, Synopsys ICC2

hardware engineering , Perl Scripting, Sta, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Power Gating, High Frequency Design, PDN Methodology, PPA Targets, Timing Signoff