CMOS Circuits, Cadence PVS, Mentor Calibre, LVS, tape-out, chip level integration verifications, Layout Design, ERC, DRC, design scripts, Cadence Virtuoso, BiCMOS circuits, analog block integration

hierarchical layout techniques, 3nm technology, custom layout design, Mentor Graphics Calibre, Totem tools, Cadence Innovus, device matching, Cadence XL, designing custom analog blocks, full-chip integration, IR drop analysis, low-parasitic layout practices