gate-level simulations, mixed-signal co-simulation tools, mixed-signal verification methodologies, Synopsys CustomSim, Cadence Virtuoso AMS Designer, PVT corner analysis, SystemVerilog UVM, AMS co-simulation platforms, digital-first verification tools, analog-digital interaction testing, SoC Verification, analog-digital interaction verification, real-number modeling RNM, SPICE simulators, Co-simulation methodologies, SPICE-level validation

Pcie, Ethernet, Emulation, RISC-V architecture, Simulation, AMBA protocols, UCIe, assertion-based verification, Uvm, coverage-driven verification, FPGA prototyping, systemverilog, constrained-random verification, formal verification, high-performance SoC architectures, SERDES, CXL, hardware software co-verification

Usb, Spi, Silicon Validation, Pcie, Scripting, design automation tools, Design Verification, RTL, Dft, Physical Design, MCU design, DMA, software validation

Frontend, Vlsi, ASIC Design, RTL, Uvm, VLSI ASIC, Director, Practice Head