Power distribution networks, Layout verification tools and methodologies, Signal integrity considerations, Analog Layout Design, Analog circuit design principles

Dac, ADC, CTS routing, Comparator, CMOS, Pll, Physical Verification, Bi-CMOS, Differential Amplifier, AMS IP integration, LDO, Charge Pump, PNR flow, PHY, SERDES, Custom Layout, SOI, Analog Mixed Signal Layout design, FinFET processes, Bandgap Ref Generators, Current Mirrors, Timing Closure, HDMI, Routing Congestion

Routing, Pvs, PERL, Tcl, R3D, PEX, LVS, Layout Techniques, Verification, Skill Programming, CAD Tools, Calibre, Analog Layout, ERC, VCAR, DRC, VSR, virtuoso

FinFET technologies, Calibre, Mixed-Signal Layout, pegasus, DRC, Physical Verification, LVS, Analog Layout Design, Cadence Virtuoso

Python Programming, analytical statistical skills, schematic design and layout review, characterization of high-speed interfaces, validating protocols, usage of bench equipment, high-speed digital validation, validating and characterizing mixed-signal analog blocks, bench software development, knowledge of IAR Keil and other tool chains, performance benchmarks

Synopsys IC Validator, Calibre DRC LVS PEX, high-speed analog and mixed-signal layout design, Custom Compiler, LVS, Cadence Pegasus, DRC, Cadence Virtuoso Layout Suite, ERC checks, 7nm FinFET technology

Vdc, custom analog layout design, EDA Tools, Antenna, ADC, Circuit Design, RV high voltage flows, noise fixes, LDO, layout validation, Charge pump, density, DRCs, scripting skills, Vlsi Design, Virtuoso XL