power integrity , Perl, Shell scripting, Python, Tcl, Physical Design signoff, power grid optimization, Cadence Voltus, electromigration concepts, Ansys RedHawk, static and dynamic IR drop analysis, EM IR analysis

redhawk , Python Scripting, Pvs, Perl, Tcl, QRC, primetime, ICC2, Tempus, Voltus, Innovus, Calibre, Physical Design, Starrcxt

block subchip level place and route for SoC, ASIC Design, Physical Design, constraints synthesis

Static Timing analysis, Perl, Tcl, Clock Planning, SoC designs, Power Plan, Digital place and route, Floor Planning, Clock Tree Synthesis, Parasitic Extraction, PnR Signoff

Python, Tcl, Design Compiler, primetime, MMMC OCV AOCV POCV timing methodologies, PT-SI crosstalk and noise analysis, SDC constraint authoring and auditing

rtl verification , simvision , Pcie, Version Control Systems, Debugging, Python, Usb, Git, Perl, AI ML fundamentals, anomaly detection, Uvm, FPGA-based verification environments, testbenches for constrained-random and metric-driven verification, vManager, EDA Tools, coverage prediction, UFS, ML techniques for regression triage, failure clustering, waveform-debug tools, systemverilog, eMMC, Cadence NCSim, DDR4, SVA

C, Os Internals, multithreading, Memory Management, Perl, Python, emulator environments, memory subsystems, verification methodologies, PCIe device controllers, FPGA validation, QEMU simulator, Spike simulator, virtualization technologies, NIC controller, multi-processor cache coherency