Unix, Shell, C, Linux, Perl, Verilog, Python, Uvm, systemverilog

static timing analysis, EDA tools for synthesis, VHDL, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, low-power design techniques, digital IC ASIC design, RTL quality tools such as Spyglass Lint CDC RDC

Verification Methodologies, NVME architecture, PCIe transport and link layers, Post silicon debug, SoC Verification, C based SoC verification, Simulation, Testbench architecture, Pattern generation

leak testing , Six Sigma., System Testing, Integration Testing, Test Automation, Design Verification, Design Validation, v&v, Medical Devices, Fda, Iso 13485, Qms, Regulatory Compliance, IQ, OQ, PQ, Equipment Qualification, Process Validation, Reliability Testing, Mechanical Testing, UTM, Torque Testing, Electro-Mechanical Products, fixture design, Laboratory Management, Vendor Qualification, Root Cause Analysis, Capa, Minitab

Dft, Physical and formal Verification, exposure to frontend and Analog processes, backend flows for MCU or low-power SoC designs

Pcie, Ethernet, Advanced verification methodologies, Mentor, Cadence, Uvm, systemverilog, Register modeling, Protocol VIP integration, PAM2, Avery, Verification of IP AMS systems, D2D, PAM4, Synopsys

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

static timing analysis, LINT, Logic Synthesis, Dft, cdc, formal verification, Cadence-based ASIC design environments, low-power design methodologies, micro-architecture development, SystemVerilog RTL design