Perl, Verilog, Shell scripting, LINT, cdc, RTL quality checks, Connectivity, SOC design, VCLP

Python Scripting, Git, PrimeTime or equivalent tools, Modern SOC tools including Spyglass, Version control systems such as Perforce, ASIC design flow, Low power digital design and analysis, Digital Design, C embedded experience, VCS simulation, Cadence Conformal, ICManage, ASIC design in sub-20nm technology nodes, Questa CDC, RTL design in Verilog, Circuit timing STA

Perl, Verilog, Shell Scripting, LINT, cdc, RTL Quality Checks, Micro Architecture Definition, Connectivity, SOC design, VCLP

Rtl Design, Subsystem design, Axi, APB, SoC integration, Microarchitecture

LINT, Sta, Synchronous design concepts, Memory operation, power analysis, SoC design flows, CMOS Circuit Design, Rtl Design, Synthesis, spyglass, device physics, CDC methodologies

Perl, Verilog, Tcl, Python, VHDL, AXI Protocols, Ethernet protocol, Ethernet IPs, Rtl Design

arm architecture , Kvm, Xen, Ras, Device Drivers, Memory Management, Docker, Pcie, Uefi, Kubernetes, crash, Linux kernel development, ACPI, ftrace, EDK2, upstreaming patches, interrupt handling, kernel logs, Scheduler, kernel subsystems, power management, secure boot, PERF, Devicetree, kgdb, U-Boot, FWTS, Acs, CI CD pipelines, NUMA, CXL, SystemReady SR