power integrity , Routing, Perl, Python, Tcl, OCV, CTS, primetime, Timing Constraints, EM IR awareness, floorplanning, SI Crosstalk, Full-Chip STA, CRPR, Cadence Tempus, SDC, Eco, MMMC, Physical Design, POCV, Clock Architecture, LVF, AOCV

power integrity , Shell, Perl, Python, Tcl, Physical Design signoff, Ansys RedHawk, IR EM analysis, Cadence Voltus

Perl, Verilog, Python, spyglass, VHDL, DDR memory controllers, PCIe protocols

Logic Design, Tcl, Python, Perl, Mentor, MBIST OCC validation flows, Synopsys, Digital Circuit Design, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, SpyGlass DFT rules, Sta, Cadence, Physical design flows, SSN design and IEEE 1687 IJTAG standards, RTL design synthesis

UNIX, Verilog, System Verilog, Debugging, Windows, Automated flows for generating RTL, Digital IP development

synopsys primetime , Synopsys FusionCompiler, Timing Signoff Tools, Physical Design Flow, SDC Proficiency, AI ML Integration, Advanced Node Experience, Advanced Clocking