Perl scripting, SoC design and implementation methodology, Synthesis, Digital ASIC design, primetime, Flow automation, Physical Design, Constraint development, Functional and DFT modes

Logic Design, Front-end design tools and methodologies, Synthesis, Static-timing closure, formal verification, Debug skills, Block-level function verification, RTL coding techniques, Gate-level simulations, Timing signoff, Micro-architecture, Verification

hardware engineering , Perl Scripting, Sta, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Power Gating, High Frequency Design, PDN Methodology, PPA Targets, Timing Signoff

synopsys primetime , Debugging, Python, Perl, Tcl, OCV, timing closure techniques, latency, multicycle paths, derates, MMMC concepts, SDC timing exceptions, timing constraints development, POCV, ECO methodologies, clock uncertainty, Case Analysis, setup hold analysis, Cadence Tempus, clock tree, path-based analysis, jitter, false paths, Timing Closure, AOCV, skew