Routing, Perl scripting, Physical Synthesis, Multi voltage design convergence, primetime, Optimization, CTS, Floor-planning, Deep sub-micron design problems, Tempus, Clocking architecture, Placement, Crosstalk avoidance, Constraint generation and validation, Power Estimation, Clock Tree Synthesis, High frequency Datapath intensive Cores

Place and Route (P&R, Tcl Scripting, Sta, Timing constraints quality assessment, SynopsysPT-SI, Signoff power analysis and optimization, Analysis, problem-solving skills, multi-voltage designs, Methodology, Cadence Tempus, timing variation aspects, Timing Analysis, EDA tool benchmarks, timing ECO flows, Debug, Block-level and chip-level signoff STA

synopsys primetime , Synopsys FusionCompiler, Timing Signoff Tools, Physical Design Flow, SDC Proficiency, AI ML Integration, Advanced Node Experience, Advanced Clocking