power integrity , Perl, Shell scripting, Python, Tcl, Physical Design signoff, power grid optimization, Cadence Voltus, electromigration concepts, Ansys RedHawk, static and dynamic IR drop analysis, EM IR analysis

redhawk , Python Scripting, Pvs, Perl, Tcl, QRC, primetime, ICC2, Tempus, Voltus, Innovus, Calibre, Physical Design, Starrcxt

Static Timing analysis, Perl, Tcl, Clock Planning, Implementation PnR Signoff, Parasitic Extraction, Floor Planning, Power Plan, Digital place and route, Constraint development, Place And Route, High speed SoC designs, Clock Tree Synthesis

Python, Tcl, Design Compiler, primetime, MMMC OCV AOCV POCV timing methodologies, PT-SI crosstalk and noise analysis, SDC constraint authoring and auditing

rtl verification , simvision , Pcie, Version Control Systems, Debugging, Python, Usb, Git, Perl, AI ML fundamentals, anomaly detection, Uvm, FPGA-based verification environments, testbenches for constrained-random and metric-driven verification, vManager, EDA Tools, coverage prediction, UFS, ML techniques for regression triage, failure clustering, waveform-debug tools, systemverilog, eMMC, Cadence NCSim, DDR4, SVA

C, Os Internals, multithreading, Memory Management, Perl, Python, emulator environments, memory subsystems, verification methodologies, PCIe device controllers, FPGA validation, QEMU simulator, Spike simulator, virtualization technologies, NIC controller, multi-processor cache coherency

Dac, Perl, Tcl, GAA nodes, ADC, Skill, FinFET, deep sub-micron CMOS, LVS, Dfm, Pll, SERDES, ERC, EMIR analysis, EDA Tools, DRC, Cadence Virtuoso