IP Program Management, timing validation, mixed signal IP design, design for test, Layout, PNR, analog logic design

Scripting Languages, Sta, Synthesis, PNR, debugging skills, ML based Solutions, Digital Implementation flow, Flow development

Scripting Languages, Synthesis, EMIR, Flow development, PNR, Digital Implementation flow, Sta

production yield targets, transistor-level design, block-level modeling, SPICE Spectre simulation, mixed-signal IC design for mobile applications, advanced packaging, top-level simulation, IC physical layout management, Cadence CAD toolset, BCD process technologies, analog mixed-signal IC design, VHDL co-simulation, system-level verification, semiconductor IC processing, hand analysis, production test solutions, IC system partitioning, top-down IC design methodologies, signal chain analysis, architectural trade-off analysis

Scripting Languages, Sta, Synthesis, Flow development, PNR, Digital Implementation flow, debugging skills, ML based Solutions

Logic Design, Static Timing Analysis, Tcl, Python, Perl, Jasper, IR drop, coverage analysis, RTL lint tools, ATE debug, Logic Synthesis, EDA Tools, Sta, RTL2GDS flow, Logic Equivalent Checking, Cadence Modus, Synthesis, post silicon validation, Verification, DFT concepts, ATPG tools, RTL implementation, debugging skills, Scan Insertion