power integrity , Routing, Perl, Python, Tcl, OCV, CTS, primetime, Timing Constraints, EM IR awareness, floorplanning, SI Crosstalk, Full-Chip STA, CRPR, Cadence Tempus, SDC, Eco, MMMC, Physical Design, POCV, Clock Architecture, LVF, AOCV

Logic Design, Perl, Python, Tcl, Sta, MBIST OCC validation flows, Cadence, Mentor, Physical design flows, SpyGlass DFT rules, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, Digital Circuit Design, SSN design and IEEE 1687 IJTAG standards, Synopsys, RTL design synthesis

power integrity , Shell, Perl, Python, Tcl, Physical Design signoff, Ansys RedHawk, IR EM analysis, Cadence Voltus

FEA tools, Debugging, Control loop theory, PCB CAD tools, power management, Circuit Design, Board level analog and digital circuit design, Data analysis using Excel or JMP, PCB schematic design, Troubleshooting

Wireshark, Zigbee, Wlan, Thread, Python, Iperf, Ellisys sniffers, Bluetooth BR, LE Audio

Servicenow, Github, Automated Testing, Microservices, Typescript, Python, Apis, Jira, Git, retrieval systems, LangGraph, multi-agent workflows, A2A, enterprise AI governance, LLM-powered applications, Vertex AI, Anthropic Bedrock, observability, cloud-native applications, event-driven systems, Production Operations, tool-calling architectures, AI agents, MCP, OpenAI