Verilog, System Verilog, DDR memory protocols, SV, HBM, Functional Verification, LPDDR, Uvm

Phase Interpolator, SERDES, Driver, Circuit Simulation, Physical Verification, Deserializer, Layout, CMOS design, Bias and Bandgap Voltage Regulators, Receiver, jitter and signal equalization techniques, High Speed Clock Distribution, Serializer, Low jitter PLL

Verilog, DDR, Test Planning, systemverilog, Uvm, Rtl Design, Functional Verification, LPDDR, HBM, Memory Subsystems, Verification Environment Development

Phase Interpolator, Cadence tool experience, CAD tools for circuit simulation, CMOS design, Bias and Bandgap Voltage Regulators, SERDES, jitter and signal equalization techniques, High Speed Clock Distribution, Low jitter PLL, layout and physical verification