redhawk , Tcl, Routing, Python, Perl, Multi-voltage domains, Foundry PDKs, UPF, Timing Closure, Signoff, Cadence Innovus, Power gating, floorplanning, primetime, Tempus, Synopsys ICC2, CPF, Voltus, Placement, Physical Design, Samsung, Low-power design techniques

Debugging, Logic Design, Sta, Circuit Design, Physical Verification, PNR, Physical Design, EDA Tools, Optimization, Rtl Design

redhawk , Perl, Python, Tcl, EMIR sign-off flows, Voltus, electromigration analysis, Totem, chip-package co-simulation, EMIR sign-off methodology, chip-package co-design, PDN planning, PDN architecture planning

static timing analysis, PVT conditions, timing budgeting, timing rollups, Timing Analysis, timing constraint adaptation, clock network optimization, timing models

Tcl, Python, PERL, Seahawk, Synthesis, ECO Timing Closure, Layout Closure, Block-level and Full-chip Floor-planning, primetime, Physical Verification, Ir, CTS, Innovus, Sta, ICC2, Physical Design, Tempus, RTL2GDSII flow, Place And Route, Timing Convergence, High Frequency Design Methodologies

Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology