Static Timing Analysis, Routing, Scripting, Cadence Genus, EM, Ir, Floor-plan Physical Implementation, primetime, Physical Design, Placement, DRC, Design Compiler, Extraction, Power-plan Synthesis, LVS, Formal Equivalence, Physical Verification, Innovus, PNR tools, ICC2, Mentor Graphics Calibre, Crosstalk Analysis, Synopsys Fusion Compiler, Apache Redhawk, Timing Closure, RTL to GDS2 flow, StarRC

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis