bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, Specman E, hierarchical memory subsystems, Debug, IP subsystem SoCs, regression systems, congestion control, AI ML accelerators, systemverilog, vector processing units, digital systems, revision control systems, full verification life cycle, constrained-random verification environments, packet processing, Verification

C, Python, Uvm, systemverilog

Unix, Bash, Svn, Git, Linux, Python, Tcl, Gate-Level Simulation, MBIST, Siemens Tessent, Test Access Networks, DFT Design Verification, ATPG, Scan Compression, Scan Architectures

C, Os Internals, multithreading, Memory Management, Perl, Python, emulator environments, memory subsystems, verification methodologies, PCIe device controllers, FPGA validation, QEMU simulator, Spike simulator, virtualization technologies, NIC controller, multi-processor cache coherency

System Verilog

Debugging Tools, Pcie, Ethernet, DSP algorithms, clock validation, memory subsystems, fuse controllers, verification methodologies, Simulation Tools, AMBA protocols, IP Subsystem SoC-level verification, microarchitecture concepts, systemverilog, coverage closure, boot flows, security validation flows, random test case development, debugging capabilities for SoC fabric, advanced computer architecture, Performance Analysis