IP Program Management, timing validation, mixed signal IP design, PNR, test layout, analog logic design

Shell, Perl, Analog Design Environment, Analog Design Flow, Virtuoso Schematic Editor, Virtuoso Layout Features

Scripting Languages, Sta, Synthesis, PNR, debugging skills, ML based Solutions, Digital Implementation flow, Flow development

Test automation, Integration And System Testing, Qualification of Vendors, Six Sigma Methodology, Exposure to Regulatory Standards Manufacturing process and procedure for, Systems Component level Verification Validation, Understanding of hardware methodologies and test best practices, IQ OQ and PQ for equipments Instruments, Design verification and validation of medical devices, Technical testing reliability experience in Plastic Connectors Products electro-mechanical, RF welding Solvent bonding process, Statistical tools like Minitab

Phase Interpolator, SERDES, Driver, Circuit Simulation, Physical Verification, Deserializer, Layout, CMOS design, Bias and Bandgap Voltage Regulators, Receiver, jitter and signal equalization techniques, High Speed Clock Distribution, Serializer, Low jitter PLL

Custom layout design, High-speed IPs, Floorplan constraints, High-speed Analog Serdes, Data converters, LVS, Scripting and automation, Analog Macros, IP integration, Pll, Physical verifications, Analog layout techniques, power management, DRC, Ageing and Reliability Compliance, Full Spectrum Verifications, Electrical check

DO-160, DO-254, Aerospace Products, Power Electronics, Pcb Layout