static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

Static Timing Analysis, Routing, Scripting, Extraction, EM, Ir, Floor-plan Physical Implementation, Physical Design, primetime, Placement, Design Compiler, DRC, Power-plan Synthesis, LVS, Cadence Genus, Formal Equivalence, Physical Verification, CTS, Innovus, PNR tools, ICC2, Mentor Graphics Calibre, Synopsys Fusion Compiler, Crosstalk Analysis, Apache Redhawk, Timing Closure, RTL to GDS2 flow, StarRC

Static Timing Analysis, Routing, Scripting, Cadence Genus, EM, Ir, Floor-plan Physical Implementation, primetime, Physical Design, Placement, DRC, Design Compiler, Extraction, Power-plan Synthesis, LVS, Formal Equivalence, Physical Verification, Innovus, PNR tools, ICC2, Mentor Graphics Calibre, Crosstalk Analysis, Synopsys Fusion Compiler, Apache Redhawk, Timing Closure, RTL to GDS2 flow, StarRC

boundary scan , Jtag, Scan Insertion, Test compression, DFT for hierarchical and multi-die designs, MBIST, DFT methodologies, Cadence Modus, ATPG, Synopsys Tetramax, LBIST, Low-power testing, Mentor Tessent

AWS, Networking, Itil, Azure, Servicenow, Gcp, hybrid infrastructure models, Synopsys, HPC environments, Siemens EDA, EDA Tools, cloud platforms, compute storage grid, Cadence, Scheduling, SRE practices

Usb, Spi, Silicon Validation, Pcie, Scripting, design automation tools, Design Verification, RTL, Dft, Physical Design, MCU design, DMA, software validation

static timing analysis, Verilog, Synthesis, SoC integration, design constraints, embedded CPUs, IP integration, systemverilog, Rtl Design, ML AI accelerators, Axi, BUS Protocols, clock power reset domains, low-power design techniques, AHB