C, System Verilog, Python, low power design, Synthesis constraint generation, Digital architecture, Debugging verification test cases, Embedded uC Designs, Synthesis, Dft, power management, Scripting of design automation, Behavioral coding, Digital RTL, Timing Analysis

Verilog, DDR, Test Planning, systemverilog, Uvm, Rtl Design, Functional Verification, LPDDR, HBM, Memory Subsystems, Verification Environment Development

redhawk , power integrity , Perl scripting, Debugging, Tcl, place-and-route, power network planning, system-level floorplanning, low-power design methodologies, Calibre, Innovus, VLSI logic design, Timing Closure, reliability EM IR analysis, Clock Tree Synthesis