hardware engineering , Perl Scripting, Sta, Circuit Level Comprehension, Low Power Flow, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, IC design, Verification, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Constraints Validation, High Frequency Design, Power Gating, PDN Methodology, PPA Targets, Timing Signoff

C, Perl, Verilog, Shell scripting, Python, Tcl, UVM assertions, systemverilog, functional and code coverage closure

Java, C, Python, ATE Char Qual Programs development, ETS800 tester platform, ATE Testing, Test Hardware Software qualification, DFT DFM standards, Analog Mixed Power products test knowledge, Test cost reduction techniques

rc extraction , Dac, Tcl, Perl, high-speed analog custom layout, Dfm, LVS, Physical Verification, EDA Tools, ADC, Cadence Virtuoso, ERC, DRC, Skill, Pll, SERDES, EMIR analysis

Logic Design, Perl, Python, Tcl, Sta, MBIST OCC validation flows, Mentor, Cadence, Physical design flows, SpyGlass DFT rules, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, Digital Circuit Design, SSN design and IEEE 1687 IJTAG standards, Synopsys, RTL design synthesis