Debugging, Scan Insertion, Timing constraints for test mode timing closure, Scan and ATPG for different fault models, LEC checks, RTL changes for DFT, Zero delay and timing simulations, Post silicon bring up, Test architecture definition, DFT ownership, IEEE1687 iJTAG compliant ICL PDL for functional manufacturing tests, Boundary scan ACJTAG IEEE 1500 implementation and verification, Low power CLP checks

Debugging, Test Planning, Simulation, systemverilog, Uvm, IP verification, Testbench development, Verification architecture, Mentoring

code coverage , closure , Ovm, Perl, Tcl Scripting, Verilog, SDF, automation, Specman, SV, assertions development, constraint randomization, RTL, Uvm, GLS, formal verification, eRM methodology, test-bench development, HVL

testbench development, UVM methodology, test plan reviews, debugging complex IP designs, systemverilog