Unix, Shell, C, Linux, Perl, Verilog, Python, Uvm, systemverilog

C, Verilog, Verdi, Xcellium, JasperGold, systemverilog

static timing analysis, LINT, Logic Synthesis, Dft, cdc, formal verification, Cadence-based ASIC design environments, low-power design methodologies, micro-architecture development, SystemVerilog RTL design

scoreboard , Verilog, System Verilog, Verification Plan, UVM Environment, Test Benches, AMBA protocols, Uvm, Assertions, Functional coverage coding, DDR protocol knowledge, Axi, RTL debugging, Code Coverage analysis, AHB

Assertions SVA, SystemVerilog SV, Timing Constraints SDC, Uvm, Functional coverage, Verification, Physical Design PD, Rtl Design

Git, Bitbucket, Clearcase, Svn, CVS, Sim Vision, Spectre X, Xcelium, Uvm, systemverilog

Tcl, Vcs, Python, Perl, Version Control, assertion-based verification, Questa, Uvm, verification methodologies, systemverilog, CI CD, RTL simulation, functional coverage

static timing analysis, Dft, low-power design methodologies, LINT, Cadence-based ASIC design environments, micro-architecture development, SystemVerilog RTL design, formal verification, Logic Synthesis, cdc