static timing analysis, Perl, Python, EDA tools for synthesis, LINT, cdc, digital design principles, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, RTL quality tools such as Spyglass, RDC, VHDL, low-power design techniques

static timing analysis, Synthesis, multi-power-domain design techniques, Simulation, Uvm, FPGA design methodologies

simvision , pipelining , Vcs, Verilog, Static Timing Analysis, Design Compiler, primetime, Xcelium, clock domain crossing, Waveform tools, VHDL, Genus, RTL design and simulation tools, Digital logic design concepts, Verdi, Synthesis tools, systemverilog, Axi, FPGA ASIC design flow, BUS Protocols, Fsms, APB, Modelsim, AHB, Low-power design techniques

C, Fpga, Soc Architecture, Verilog, Scripting Languages, systemverilog, digital logic design principles, logic synthesis techniques, RTL design concepts, ASIC design methodologies, emulation platforms, low-power design techniques, assertion-based formal verification

Version Control Systems, Tcl, Verilog, static timing analysis, Perl, Git, Shell, Perforce, Python, Scripting Languages, AHB, LEC, systemverilog, EDA Tools, LINT, Rtl Design, Synthesis, APB, Axi, SoC Architecture Design, SoC Integration, cdc, formal verification, AMBA protocols, Simulation