Regression Analysis, Cadence Xcelium, Top-Level Verification, wreal Modeling, model validation, Cadence VIVA, Schematic-Level Correlation, Uvm, Coverage-Driven Verification, Analog Circuit Fundamentals, Waveform Debug, SV-RNM, Verification Planning, Cadence ADE Assembler, Simulation Debug, SoC AMS Verification, Digital Design Flow, Mixed-Signal SoC Integration, systemverilog, Verilog-AMS, Cadence SimVision, Cadence Virtuoso, AMS Verification Methodology, Mixed-Signal Verification

Dsp, C, Debugging, Verilog, System Verilog, Systemc, Gate-Level Simulation, Power aware verification, Uvm, Assertions, Asic Design Verification, NPU, Processor Architecture, formal verification, HVL, Digital Design, Assembly

C, Ovm, virtualization, Tcl, Python, Perl, debugging test failures, cache controllers, Uvm, x86 assembly, SystemVerilog Assertions, systemverilog, Client Server centric CPU features, FPGA HW platforms, memory coherency, Validation using Emulation, semi randomized test generators, validation strategy development, coverage driven Validation methodologies, power management