Schematic design, Production data releases, design for manufacturing, Altium Designer, EMC optimizations, Siemens Xpedition, Electrical hardware design, Thermal concept, Design to Cost, Low voltage power electronics design, Pcb Layout, and functional safety development processes, component selection

hierarchical layout techniques, 3nm technology, custom layout design, Mentor Graphics Calibre, Totem tools, Cadence Innovus, device matching, Cadence XL, designing custom analog blocks, full-chip integration, IR drop analysis, low-parasitic layout practices

IR drop, LVS, DRC, Cadence Virtuoso XL, electromigration, CMOS IC mask design, PEX, Calibre, coupling capacitance, device and signal matching

Phase Interpolator, CAD tools for circuit simulation, CMOS design, Bias and Bandgap Voltage Regulators, SERDES, jitter and signal equalization techniques, High Speed Clock Distribution, Low jitter PLL, layout and physical verification

PERL, Python, Tcl, Ir, Mentor, Cadence, LVS, EM Signoff, Synthesis, Formal Equivalence, DRC, Synopsys

Phase Interpolator, CAD tools for circuit simulation, CMOS design, Bias and Bandgap Voltage Regulators, SERDES, jitter and signal equalization techniques, High Speed Clock Distribution, Low jitter PLL, layout and physical verification

Pcie, Multilayer PCB designs, SerDes signals, DDRx, PCB layout concepts, High-Speed PCB Design, Complex PCB Design, High-speed routing techniques

vehicle safety , control panel design , wiring diagrams , Autocad Electrical, HVDC components, Functional safety, Cable harness design, Inverters, Electrical System Design, Electrical schematics, Relays, CAN bus layout, Layout drawings, DC-DC converters, Teamcenter

test mode timing constraints definition, DFTMax, Cadence Encounter Test, simulating test vectors, Transition delay test coverage analysis, ASIC DFT, Genus Synopsys, TetraMax, equivalence check DFT DRC rules, DFT concepts, timing fixes, Scan Insertion, ATPG coverage analysis

boundary scan , Jtag, Perl, Python, Tcl, MBIST, Siemens Tessent, Insertion Coverage Analysis, Static Verification, Synopsys TestMAX, TetraMax, Cadence Modus, ATPG, Scan Compression, DRC Rule Checks, LBIST, EDA Tool Proficiency, DFT Architecture