bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, Specman E, hierarchical memory subsystems, Debug, IP subsystem SoCs, regression systems, congestion control, AI ML accelerators, systemverilog, vector processing units, digital systems, revision control systems, full verification life cycle, constrained-random verification environments, packet processing, Verification

Unix, Usb, Jtag, Linux, Perl, Pcie, Ethernet, System Verilog, Python, UVM methodology, Design for Debug, TSN, ARM based SoC verification