Tcl, Shell scripting, Python, Vcs, Perl, Uvm, NC-Sim, systemverilog

gate-level simulations, mixed-signal co-simulation tools, mixed-signal verification methodologies, Synopsys CustomSim, Cadence Virtuoso AMS Designer, PVT corner analysis, SystemVerilog UVM, AMS co-simulation platforms, digital-first verification tools, analog-digital interaction testing, SoC Verification, analog-digital interaction verification, real-number modeling RNM, SPICE simulators, Co-simulation methodologies, SPICE-level validation

SoC Productization, Ate, Dft, System Validation, DFX methodologies, Emulation, Silicon Embedded Firmware, Silicon Bring-up, Debug, Post-Silicon Validation, Manufacturing Test

Usb, C, Pcie, Ethernet, I2c, Python, validation methodologies, Flash architecture, emulation environments, ARM processors, lab test equipment, SERDES, NVMe storage protocols, FPGA prototyping flows, DDR5, LPDDR, I3C

Usb, Spi, Silicon Validation, Pcie, Scripting, design automation tools, Design Verification, RTL, Dft, Physical Design, MCU design, DMA, software validation

Frontend, Vlsi, ASIC Design, RTL, Uvm, VLSI ASIC, Director, Practice Head

static timing analysis, Verilog, Synthesis, SoC integration, design constraints, embedded CPUs, IP integration, systemverilog, Rtl Design, ML AI accelerators, Axi, BUS Protocols, clock power reset domains, low-power design techniques, AHB

Security Solutions, AI-ready Ethernet Fabrics, Cloud Networking Observability, Campus Wi-Fi, GSP Model, Network Security Automation, networking infrastructure, Data Center Switching