Senior Physical Design EMIR Engineer

Exp-3-10yrs

Location-Bengaluru

Role Overview:

We are seeking a Senior Physical DesignEMIR Engineer to drive power integrity, IR drop, and electromigration analysis for advanced SoC designs. The ideal candidate will have strong expertise in EMIR sign-off methodology, PDN planning, and chip-package co-design, along with the ability to lead and mentor a team of engineers.

Experience :- 3 Years to 10 Years

Key Responsibilities:

Lead IR drop, electromigration, and power integrity analysis across multiple blocks and full-chip designs.
Define, implement, and optimize EMIR sign-off flows using industry-standard tools (Redhawk, Voltus, Totem, etc.).
Drive PDN architecture planning and collaborate with Physical Design teams to ensure robust power delivery.
Perform chip-package co-simulation to validate power distribution across die, package, and board.
Review and analyze EMIR reports, debug issues, and provide recommendations to closure.
Own and automate EMIR flows using Python/Perl/TCL scripting.
Collaborate with cross-functional teams (RTL, PD, Verification, Packaging) for design convergence.
Mentor and guide junior engineers in EMIR methodologies and best practices.

About Us:

LeadSoC Technologies offers cutting edge Engineering Design services in VLSI and Embedded Systems. We have been growing rapidly over the last 7 years to meet the evolving needs of the Semiconductor, Automotive, Telecom and Consumer Electronics segments.

Our End-to-End VLSI design services span Micro Architecture to Tape Out and beyond with Post Silicon support. We have been involved in co-development of multiple SOC releases for our clients. LeadSoC has in house VLSI labs equipped with state of art tools (from leading EDA OEM's) for grooming talent. We work on SOC's, FPGA and ASIC platforms in areas spanning Digital Front End Design & Verification, Back End Design (RTL=> GDS), Analog & Custom Design & Verification. We also work on RF & Board Design for OEMs.

Our Software practice works in areas spanning Firmware design, Hardware Abstraction, Kernel Space & User space design. We work on both bare metal and RTOS/Linux like platforms across x86, ARM, MIPS & Power PC architectures across multiple chipsets.

Our presence in Concept to Manufacturing, spans across a broad spectrum of capabilities including Board Design, Platform Software solutions (Boot Loader, Bare Metal Firmware, Drivers/BSP, Abstraction layers), Middleware (Stacks, Frameworks, diagnostics), Target application, HMI (industry standard frameworks), IoT and Cloud (AWS, GCP, Azure) applications and V&V services.

We have an embedded Software COE with in-house Labs, powered by open-source tool chain equipped with variety of reference boards. This environment enables our engineers to play while they learn. It also creates an environment for the engineers to ideate / create reference Solutions, POC designs.

Our teams have been involved in providing frameworks for On-board Diagnostics, Manufacturing diagnostics, Post & Pre-Silicon Validation and Performance Optimization for products based on Linux / RTOS platforms. We have also worked on migrating stacks from legacy to NextGen platforms.

http://www.leadsoc.com

Senior Physical Design Engineer