snoops, Coverage, SystemVerilog UVM assertions, ARM AMBA CHI, Ordering, caches, cache coherency concepts, MESI, SystemVerilog UVM, load store atomics, multicore CPU architectures, MOESI

C, Ovm, virtualization, Tcl, Python, Perl, debugging test failures, cache controllers, Uvm, x86 assembly, SystemVerilog Assertions, systemverilog, Client Server centric CPU features, FPGA HW platforms, memory coherency, Validation using Emulation, semi randomized test generators, validation strategy development, coverage driven Validation methodologies, power management