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Showing 4 jobs
Skills:
power optimization , Static Timing Analysis, power analysis, low power design techniques, SoC integration, Design-for-Test, constraints development for Physical Design implementation, Design-for-Debug, SoC Debug architectures
Skills:
Verilog, VHDL, power analysis tools, low-power design techniques, systemverilog, logic synthesis techniques
Skills:
Fpga, Matlab, ASIC, VHDL, Simulink
Skills:
Vcs, Tcl, Verilog, System Verilog, Python, Perl, Sec, Questa, spyglass, LINT, Xcelium, cdc, Jasper-FPV, Questa CDC, RDC
