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Showing 5 jobs

Skills:
Mentor, Uvm, firmware interaction, Synopsys, AMs, systemverilog, Cadence, Siemens, Calibration and link training flows, Register models, industry VIPs, Avery, SERDES
Skills:
Verilog, Unix, Python, Perl, Shell, Linux, systemverilog, Uvm
Skills:
IP SoC verification, ASIC-SoC design verification, systemverilog
Skills:
Dsp, System Verilog, Assembly level testcases, formal verification, Assertions, Digital Design, Uvm, Asic Design Verification, Processor Architecture, NPU, Debug, Gate-Level Simulation, Power aware verification
Skills:
C, Perl, Verilog, Shell scripting, Python, Tcl, UVM assertions, systemverilog, functional and code coverage closure
