Mentor, Uvm, firmware interaction, Synopsys, AMs, systemverilog, Cadence, Siemens, Calibration and link training flows, Register models, industry VIPs, Avery, SERDES

Verilog, Unix, Python, Perl, Shell, Linux, systemverilog, Uvm

IP SoC verification, ASIC-SoC design verification, systemverilog

Dsp, System Verilog, Assembly level testcases, formal verification, Assertions, Digital Design, Uvm, Asic Design Verification, Processor Architecture, NPU, Debug, Gate-Level Simulation, Power aware verification

C, Perl, Verilog, Shell scripting, Python, Tcl, UVM assertions, systemverilog, functional and code coverage closure