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Showing 10 jobs
Skills:
Fpga, Perl, Python, object-oriented programming, RTL, test plan development, Uvm, emulation platforms, systemverilog, automation scripts
Skills:
IP SoC verification, ASIC-SoC design verification, systemverilog
Skills:
Regression Analysis, Cadence Xcelium, Top-Level Verification, wreal Modeling, model validation, Cadence VIVA, Schematic-Level Correlation, Uvm, Coverage-Driven Verification, Analog Circuit Fundamentals, Waveform Debug, SV-RNM, Verification Planning, Cadence ADE Assembler, Simulation Debug, SoC AMS Verification, Digital Design Flow, Mixed-Signal SoC Integration, systemverilog, Verilog-AMS, Cadence SimVision, Cadence Virtuoso, AMS Verification Methodology, Mixed-Signal Verification
Skills:
bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, Specman E, hierarchical memory subsystems, Debug, IP subsystem SoCs, regression systems, congestion control, AI ML accelerators, systemverilog, vector processing units, digital systems, revision control systems, full verification life cycle, constrained-random verification environments, packet processing, Verification
Skills:
Perl, Verilog, Python, System Verilog, Tcl, Dft, DV, Uvm
Skills:
Perl, Pcie, Ethernet, Shell scripting, Python, CHI, Ace, USB 3.x, RISC-V, Uvm, Assertions, systemverilog, Axi, USB4, CXL, DDR5, DDR4, SVA
Skills:
Perl, Verilog, System Verilog, Python, Tcl, Mentor Questa, Cadence Xcelium, CHI, Ace, Synopsys VCS, Axi, AMBA, VHDL, RISC-V instruction set architecture, APB, UVM-based testbenches
Skills:
Pcie, Perl, Python, AMBA, Axi, APB, AHB, System Verilog assertions, systemverilog
Skills:
Perl, Verilog, Python, Synopsys VCS, Cadence Incisive, VHDL, Modelsim, Uvm
Skills:
Unix, Bash, Svn, Git, Linux, Python, Tcl, Gate-Level Simulation, MBIST, Siemens Tessent, Test Access Networks, DFT Design Verification, ATPG, Scan Compression, Scan Architectures
