C, Os Internals, multithreading, Memory Management, Perl, Python, emulator environments, memory subsystems, verification methodologies, PCIe device controllers, FPGA validation, QEMU simulator, Spike simulator, virtualization technologies, NIC controller, multi-processor cache coherency

Noc, C, Perl, Verilog, Python, power analysis, Synthesis, processor design, low power design techniques, arithmetic units, SoC designs, memory hierarchies, design of IPs and Subsystems, systemverilog, integration flows, Asic Design Verification, Fabrics, accelerators, micro-architecture, bus architectures

Embedded C, Fpga, C, Spi, DDR, Pcie, Sata, Usb, BIOS, Uefi, System Architecture, emulation verification, Post Silicon Validation, Memory subsystem, technical debug, Security Protocols, NPU, power management, emulation platforms, SoC IP level Power Management, Validation, low power design, validation strategy, high speed IO peripherals, Axi, MIPI, SoC Verification

Embedded C, Fpga, C, Spi, DDR, Pcie, Sata, Usb, Uefi, BIOS, Pci, System Architecture, emulation verification, Post Silicon Validation, Memory subsystem, technical debug, Security Protocols, NPU, power management, emulation platforms, SoC IP level Power Management, Validation, low power design, validation strategy, high speed IO, MIPI, Axi, SoC Verification

Jenkins, Github, Git, Pytest, C, Verilog, Python, System Verilog, Git actions

power delivery , Debugging, Logic Design, High-speed IO protocols, Signal Integrity, GPU and SoC system qualification, Silicon and board bring up validation

System Architecture, Usb, Embedded C, Uefi, Spi, C, Fpga, BIOS, Sata, Pcie, DDR, validation strategy, MIPI, Post Silicon Validation, high speed IO peripherals, Axi, emulation verification, Memory subsystem, Security Protocols, SoC Verification, technical debug, emulation platforms, SoC IP level Power Management, Validation, low power design, NPU, power management