arm architecture , power delivery , Digital Logic Design, Uefi, Computer Architecture, C Programming, Analog circuitry, Linux boot sequence, DRAM functionality, JEDEC standards, DDR validation, SoC package board design, Bootloader firmware development, DFI specifications, Signal Integrity

Pcie, C, Python, Scripting Languages, DDR, Soc Architecture, hardware software integration, Power Characterization, Emulation, RTL design verification

C, Fpga, Usb, Embedded C, Linux, BIOS, Pcie, Uefi, emulation verification, Memory subsystem, Security Protocols, SoC IP level Power Management flow, SoC Verification, ARM SoC Architecture, Windows Operating Systems, emulation platforms, Validation, high speed IO peripherals, low power design, Pre-Silicon Validation Experience, NPU, power management

Java, BigQuery, Hadoop, Flume, Kafka, Dataproc, Mapreduce, Pig, Hive, Javascript, Spark, DataFlow, Python, Genomics, Go, Pub Sub, Dataprep, Cloud Bigtable, Cloud SQL, Datalab

Embedded C, Fpga, C, Spi, DDR, Pcie, Sata, Usb, BIOS, Uefi, System Architecture, emulation verification, Post Silicon Validation, Memory subsystem, technical debug, Security Protocols, NPU, power management, emulation platforms, SoC IP level Power Management, Validation, low power design, validation strategy, high speed IO peripherals, Axi, MIPI, SoC Verification

Embedded C, Fpga, C, Spi, DDR, Pcie, Sata, Usb, Uefi, BIOS, Pci, System Architecture, emulation verification, Post Silicon Validation, Memory subsystem, technical debug, Security Protocols, NPU, power management, emulation platforms, SoC IP level Power Management, Validation, low power design, validation strategy, high speed IO, MIPI, Axi, SoC Verification

Assembly Language, Software Development Life Cycle, X86, Make Files, Memory system architecture, linkers, SoC architecture paradigms, C language expertise, Memory barriers, Compilers, Multi-threaded applications, JTAG based debuggers, FPGA emulation platforms, Pipelining of memory systems, Weakly ordered memory model, Silicon debug hooks, PowerPC CPU, ARM Cortex-A7, Cross compilers, power management