static timing analysis, Perl, Tcl, Makefile scripting, Synthesis, physical design CAD flow, Mentor Calibre, Power Distribution, Cadence Innovus, Cadence Genus, Floor Planning, physical design verification

Fpga, Logic Design, Verilog, Uvm, Timing Constraints, TCL scripts, regression frameworks, Timing Analysis, Power product design, System-Verilog, RTL Coding, Functional Verification, Sta, micro-architecture, ATPG generation, formal verification, synthesis scripts, Synthesis, ABV, design constraints, Digital Verification, Scan Insertion

smartsheet , JIRA, Confluence, Silicon Validation, STA Signoff, VLSI SoC chip design lifecycle, Physical Design, Rtl Design, Microsoft Project, Program Management, Design Verification, Dft

redhawk , Tcl, Perl, Scripting, Physical design of block level, Physical design fundamentals, Pt, Implementation STA, Signoff tool, Fusion Compiler, Physical Verification, Calibre, Innovus, PnR cycle, PNR tools, ICC2, Prime time, Signoff tools, Digital Electronics

Scripting, Python, Routing, Tcl, CTS, primetime, 3D IC, Cadence, LVS, IR Drop, Innovus, Calibre, Physical Verification, HBM, Placement, Si, Chiplets, floorplanning, EM, Full-Chip Physical Design, Advanced Packaging, Timing Closure, DRC, EDA Tools, 2.5D, Advanced nodes 7nm or below, Synopsys ICC2

Logic Design, silicon design, physical implementation, PPA trade-offs, EDA Tools, Design Methodologies, Verification, Circuit Design

Tcl, Python, Synopsys ICV, Device Modelling, Ansys RHSC, Siemens Calibre, Cadence Pegasus, Simulation Tools, TVF, Reliability verification, Parasitic Extraction, Cadence Voltus

Soc, Dft, end-to-end ASIC turnkey solutions, physical design verification, ASIC, semiconductor design, spec definition, IC services, tape-out support, RTL