Networking, Pcie, Test Methodologies, Ethernet, Axi, AMBA

digital filter blocks (CIC, reset domain crossing (RDC), clock domain crossing (CDC), static timing analysis (STA), IIR), Verilog, RTL-to-GDSII design flow, Synthesis, synchronizers, arbitration logic, systemverilog, Pipelines, handshaking, digital RTL design, FIFOs, Fsms, mixed-signal design concepts, FIR

C++, Perl, Python, RTL Verilog, Uvm, systemverilog, SVA

Verilog, Scripting Languages, Ethernet, systemverilog, Uvm, low power design, Functional Verification, Testbench Development, Simulation Tools, Debugging Techniques, Timing Analysis

Integration, System Verilog, Test Planning, testbench stimulus agent monitor checker development, ASIC Design, Verification, coverage driven constraint random verification, Uvm, Validation, c based reference model

Computer Architecture, Verilog, System Verilog, Python, Logic Design, Tcl, Synthesis and Physical Design flows, Digital Design Techniques, device physics