Logic Design, power analysis, Synthesis, multidimensional designs, system simulation, ASIC development, Place And Route, module interfaces

Static timing analysis, Shell scripting, System Verilog, Test-bench components, Verification environment, Synthesis timing analysis, RTL linting, Uvm, Timing Closure, RDC techniques, Dft, Synthesis, FPGA kits, Verilog RTL design, Timing Constraints, Gate level verification, Simulation, Hardware Verification

Python, Rhino.Inside.Revit, Rhino, STAAD.Pro, Etabs, Grasshopper, Autocad, Dynamo, Sap2000