Perl, Python, Tcl, Clock domain partitioning, Block and subsystem-level physical design flows, primetime, Power integrity and power-aware physical implementation, Clock gating, Fusion Compiler, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

Perl, Python, Tcl, Physical Design, Sta, ASIC Implementation, EM, PDN, Ir, make

PPA Optimization, RTL Co-Optimization, Physical Design, primetime, Tempus, Synopsys Fusion Compiler, Cadence Innovus, EDA Tools

Static Timing Analysis (STA), Fpga, Synthesis, ASIC design flows and methodology, low power design implementation, power gating, sign-off optimizations, multi-voltage domains, deep sub-micron technology, Physical Design, IP integration, DSP systems, sign-off convergence, SOC place and route, Circuit Design, device physics

Tcl Scripting, Python, Perl, floorplanning, setup hold violations, PVT analysis, full-chip physical design, PPA optimization, clock optimization, IR EM-related issues, Cadence Innovus, Placement, SDC constraints, CTS, signoff, routing optimization, clock-tree synthesis, MMMC, Signal Integrity, Timing Closure, congestion, timing ECOs, STA timing analysis

redhawk , Synopsys ICC2, PNR and signoff tools, Cadence Innovus, Physical Verification, IR EM mitigation, PDN methodology, floorplanning, STA constraints, physical design implementation, primetime, Tempus, Voltus