Static Timing, Routing, Physical Verification, Synthesis, Power Efficiency, Custom Clocking, Physical Design, floorplanning, Placement, Formal Equivalency, IR-Drop

routing, Verilog, Floor Planning, VHDL, Placement, Physical Verification, Clock Tree Synthesis, RTL to GDS flows

redhawk , Scripting, Tcl, Perl, routing, Shell, Python, floorplanning, Physical Verification, variability analysis, EDA Tools, EM, Ir, Placement, primetime, Synopsys ICC2, Cadence Innovus, CTS, low-power design, automation skills, Voltus, Si, Timing Closure, ASIC SOC physical design implementation, StarRC

redhawk , power integrity , Debugging, Tcl, Perl scripting, power network planning, low-power design methodologies, reliability EM IR analysis, place-and-route, VLSI logic design, system-level floorplanning, Calibre, Innovus, Timing Closure, Clock Tree Synthesis