Git, Svn, Verilog, Tcl, Python, Perl, Clocking Resets CDC, EDA Tools, CXL.mem, systemverilog, CXL.io, CHI, Ace, Rtl Design, LINT, performance optimization, Synthesis, PCIe protocol architecture, CXL.cache, RDC, AMBA protocols

Tcl, Python, Perl, systemverilog, CXL.io, CHI, Ace, CXL.mem architectures, cdc, debugging functional and performance issues, Verilog RTL development, performance optimization, LINT, PCIe protocol architecture, CXL.cache, RDC, AMBA protocols