rtl verification , Gate-Level Simulation (GLS), Ovm, SoC Verification, Sub-System Verification, Chip-Level Verification, Cluster-Level Verification, Timing GLS, Uvm, systemverilog, Microprocessor, Microcontroller Architecture, Peripheral Verification

Java, Automation testing, Manual Testing, Test Design, Squish, Test analysis, Python, Verification and validation plans, Traceability Matrices, Installation Operational Performance Qualification Protocols, Design verification and validation of medical devices, Reliability theory and analysis

test procedures , Performance Testing, JIRA, ALM, Test fixture creation, Iec, Iso, Traceability Matrices, Design Verification, Minitab, System Verification testing, FDA MDD MDR, Data Analysis

protocol stack , Gerrit, Networking, Qos, Ip Routing, Python, Java, Bash, Jenkins, Git, Linux, Integration, Lte, switching, latency, QoE, CI CD, system-level verification, traffic generation, KPIs, throughput, Deployment, Resource Utilization, 5G New Radio NR, Channel emulators, Troubleshooting, RAN architecture, Test Tools, Performance Analysis

Risk Mitigation, DA, EU, Iso

Perl, Python, System Verilog, Building test benches from scratch, Zebu, Veloce, ASIC verification using UVM, Palladium, HAPS

System Verilog, Gate Level Simulations, Building test benches, ASIC verification using UVM, formal verification