FinFET technologies, Calibre, Mixed-Signal Layout, pegasus, DRC, Physical Verification, LVS, Analog Layout Design, Cadence Virtuoso

cadence schematic capture , Cadence Tools, Memory layout design, AI automation in layout, CALIBRE, ElectroMigration, Hercules, SKILL Programming, Physical Verification, LVS, ERC, DRC, Script Programming, Antenna, Chip Integration, Floor-planning, Hierarchy layout

Fpga, C, Pcie, Ethernet, Python, Test result analysis, Verilog RTL coding, ESD Latchup HTOL tests, Analyzers, Oscilloscopes, Peripheral chips, High speed SERDES, High speed interface design techniques, UCIe, Debug skills, Lab automation scripts, Schematic and layout level, Bit Error Rate Testers, CXL, Electrical and Protocol Interoperability and Compliance test suites, Protocol Exercisers, Post-Silicon PHY Systems Interop and Compliance testing, Signal and Power integrity checks

hierarchical layout techniques, 3nm technology, custom layout design, Mentor Graphics Calibre, Totem tools, Cadence Innovus, device matching, Cadence XL, designing custom analog blocks, full-chip integration, IR drop analysis, low-parasitic layout practices

Integrated circuits, Analog Layout Design, Design Rule Checks

shielding , Tcl Scripting, Perl, Layout dependent effects, Signal shielding, Semiconductor device physics, Cadence Virtuoso XL VXL, Latchup, Skill, Parasitic noise, Calibre, EMIR, Noise isolation, Esd, Supply consideration, Isolation, Well’s substrates, Layout matching, Double patterning, Device matching

CMOS Circuits, Mentor Calibre, Cadence PVS, LVS, tape-out, layout editing tools, productivity-enhancing tools, chip-level floorplanning, ERC, chip-level integration verification, DRC, design scripts, Cadence Virtuoso, BiCMOS circuits, analog block integration