cadence schematic capture , Cadence Tools, Memory layout design, AI automation in layout, CALIBRE, ElectroMigration, Hercules, SKILL Programming, Physical Verification, LVS, ERC, DRC, Script Programming, Antenna, Chip Integration, Floor-planning, Hierarchy layout

FinFET technologies, Calibre, Mixed-Signal Layout, pegasus, DRC, Physical Verification, LVS, Analog Layout Design, Cadence Virtuoso

hierarchical layout techniques, 3nm technology, custom layout design, Mentor Graphics Calibre, Totem tools, Cadence Innovus, device matching, Cadence XL, designing custom analog blocks, full-chip integration, IR drop analysis, low-parasitic layout practices

Electrical check, Scripting and automation, IP integration, Custom layout design, Physical verifications, LVS, Analog layout techniques, Ageing and Reliability Compliance, Data converters, Floorplan constraints, Analog Macros, power management, DRC, Full Spectrum Verifications, High-speed Analog Serdes, Pll, High-speed IPs

power management, Scripting and automation, IP integration, Custom layout design, Physical verifications, LVS, Analog layout techniques, Ageing and Reliability Compliance, Data converters, Floorplan constraints, Analog Macros, DRC, Electrical check, Full Spectrum Verifications, High-speed Analog Serdes, Pll, High-speed IPs

PEX, R3D, floorplanning, Mentor Graphics Calibre, LVS, Dfm, Analog layout techniques, OA PVS, Virtuoso XL, DRC, Parasitic management, Advanced CMOS BCD technologies, Cadence Virtuoso, Device matching, ESD protection

OASIS, Verilog, Python, Shell, Perl, Tcl, PERC, LVS, CDL, Dfm, SVRF-based automation, XOR methodologies, antenna density, ASIC physical verification, Spice, Cadence Pegasus, DEF, LEF, Siemens Calibre nmDRC, metal-fill, ERC, DRC, Synopsys ICV, GDSII

Python, Tcl, timing sign-off, PDV, Physical Design, place-and-route analysis, Cadence Innovus, Siemens Mentor Calibre, advanced technology nodes 5nm or lower