power integrity , Routing, Perl, Python, Tcl, OCV, CTS, primetime, Timing Constraints, EM IR awareness, floorplanning, SI Crosstalk, Full-Chip STA, CRPR, Cadence Tempus, SDC, Eco, MMMC, Physical Design, POCV, Clock Architecture, LVF, AOCV

power integrity , Shell, Perl, Python, Tcl, Physical Design signoff, Ansys RedHawk, IR EM analysis, Cadence Voltus

FEA tools, Debugging, Control loop theory, PCB CAD tools, power management, Circuit Design, Board level analog and digital circuit design, Data analysis using Excel or JMP, PCB schematic design, Troubleshooting

Wireshark, Zigbee, Wlan, Thread, Python, Iperf, Ellisys sniffers, Bluetooth BR, LE Audio

Servicenow, Github, Automated Testing, Microservices, Typescript, Python, Apis, Jira, Git, retrieval systems, LangGraph, multi-agent workflows, A2A, enterprise AI governance, LLM-powered applications, Vertex AI, Anthropic Bedrock, observability, cloud-native applications, event-driven systems, Production Operations, tool-calling architectures, AI agents, MCP, OpenAI

Perl, Verilog, Python, spyglass, VHDL, DDR memory controllers, PCIe protocols

Logic Design, Tcl, Python, Perl, Mentor, MBIST OCC validation flows, Synopsys, Digital Circuit Design, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, SpyGlass DFT rules, Sta, Cadence, Physical design flows, SSN design and IEEE 1687 IJTAG standards, RTL design synthesis