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Showing 4 jobs
Skills:
Python, scoreboarding, Mentor Questa, Cadence Xcelium, AXI protocol, GLS, SystemVerilog UVM, Synopsys VCS, memory controller architecture, assertions SVA, DDR protocol JEDEC specifications, functional coverage
Skills:
Ethernet, Pcie, Synopsys, Uvm, advanced verification methodologies, systemverilog, Mentor, Cadence, PAM4, Register modeling, D2D, protocol VIP integration, Avery, PAM2
Skills:
Shell, Pcie, Perl, Arm, Python, Tcl, MCU, AMBA, Axi, UCIe, systemverilog
Skills:
Tcl, Verilog, Python, Perl, Uvm, SVA, VHDL, systemverilog
